The present invention relates to semiconductor integrated circuits and more particularly to an internal power-supply voltage supplier adapted for high density memory devices, which converts external power-supply voltage into an internal power-supply voltage having a desired potential.
With the rapid progress of the fabrication technologies for semiconductor memory devices, integration has also increased. More specifically, and with reference to the present application, there has been adapted an internal power-supply voltage supplier for ensuring that memory devices fabricated with a narrow line width for each signal path on a chip can have a high reliability and be stabilized for various operational voltages applied thereto. That is, by installing on-chip an internal power-supply voltage supplier, regardless of the external power-supply voltage a constant voltage is applied to the interior of the memory device. It is well known in the art that such an internal voltage drop technique is generally used. However, this technique necessarily includes an internal power driver for receiving an external power-supply voltage and outputting a desired internal power-supply voltage, a reference voltage generator for receiving the external power-supply voltage and generating a reference voltage to determine whether the received voltage is in a desired level, and a detector for detecting whether the internal power-supply voltage output from the internal power driver maintains the desired level. As known from the above described configuration, the internal power-supply voltage supplied to the interior of a chip is provided through the internal power driver, which has to supply an accurate and stable internal power-supply voltage from the application of the external power-supply voltage.
FIG. 1 is a circuit diagram illustrating a conventional internal power-supply voltage supplier. In the overall circuit configuration of the figure, it can be appreciated that there is provided a comparator comprised of differential amplifiers having a level shifting reference signal SREF and the internal power-supply voltage int.Vcc. Signal REF is a reference signal output from the reference voltage generator, for example, such as a band gap reference circuit BGR, which signal is supplied at a constant voltage regardless of an operational voltage and variation of a temperature. The use of BGR circuit techniques are disclosed in Korean patent application No. 91-10193 entitled "A Reference Voltage Generating Circuit", filed by the applicant of the present invention, and in U.S. Pat. No. 4,795,918 issued to Suresh M. Menon. The signal SREF is level-converted from the signal REF to have a higher level than that of the signal REF. That is, since a voltage level of the signal REF is lower than a level of internal power-supply voltage int.Vcc, the signal SREF is made by raising a reference voltage level by a constant ratio.
Operational features of the configuration of FIG. 1 will be described in the following description.
Upon power-up of a chip, the external power-supply voltage ext.Vcc is supplied. By the current flow of an NMOS transistor 10 to which the signal SREF is supplied, a voltage of a connecting node 6 is discharged in the direction of a ground potential GND. Therefrom, a PMOS driver 18 is turned on and a voltage is charged to an internal power node 20 as the output node thereof. When the voltage level charged to the internal power node 20 is raised to a desired level and thus reaches a higher level than that of the signal SREF, the internal power-supply voltage int.Vcc is maintained at the desired level by a switching operation of NMOS transistor 12. In the meanwhile, the configuration of the internal power driver has a feature such that, if the output of the comparator is fed back in the negative direction, the input of the comparator is virtual-shorted (V+=V-, I=0). Accordingly, the voltage of the signal SREF is equal to the internal power-supply voltage int.Vcc and the power flowing into the whole chip is supplied through the PMOS driver 18. Since the size of the PMOS driver 18 driving the whole internal power is large and current levels of differential amplifiers 2,4,10,12 and 16 driving the PMOS driver 18 are relatively low due to the limitation of the stand-by current, an undesirably large period of time is required until a gate control signal applied to the gate of the PMOS driver 18 is varied by a voltage difference between the reference signal SREF and the internal power-supply voltage int.Vcc. Thus, at critical times when the chip operates, the internal power-supply voltage int.Vcc is excessively shaken. For example, supposing that the chip is in a non-selection state, since there is little current flow in the internal power node 20, so that connecting node 6, at the gate of the PMOS driver 18 has a voltage capable of enabling the PMOS driver 18 to be turned off. However, if the chip is changed from the non-selection state to a selection state, the current flow in the internal power node 20 is drastically increased, so that the connecting node 6 can turn on the PMOS driver 18. Since a constant period of time .tau.1 is required until current is supplied to the internal power node 20, the level of the internal power-supply voltage int.Vcc goes down during the time .tau.1, and thus the chip performance is degraded. On the other hand, if the chip is changed from the selection state to the non-selection state, the voltage level of the connecting node 6 for controlling the current flowed in the PMOS driver 18 suddenly decreases such that abruptly no current flows through the PMOS driver 18 as shown in FIG. 2C. Thus, the level of the internal power-supply voltage int.Vcc during the time .tau.1 is kicked-up toward a level of the external power-supply voltage ext.Vcc.
FIGS. 2A to 2D are waveform diagrams illustrating the operational characteristics of the internal power-supply voltage supplier of FIG. 1. Referring to FIG. 2A, it is noted specifically that the level of the internal power-supply voltage at time t1 is kicked-up towards the level of the external power-supply voltage.
In the conventional internal power driver of FIG. 1, it takes a considerable time for the internal power-supply voltage level kicked-up by the above described process to be discharged as a stand-by current. This may also cause a reliability problem since the internal power-supply voltage int.Vcc level of the chip is maintained for a longer time than intended. Furthermore, whether a rising period time of a chip selection signal CS is long or short, as illustrated in FIG. 2B, can undesirably cause a change in the internal speed. In addition, in the conventional internal power driver, because gains of the differential amplifiers 2,4,10,12 and 16 are decreased when the level of the external power-supply voltage ext.Vcc is similar to that of the internal power-supply voltage int.Vcc, the period of time .tau.1 becomes increased as shown in FIG. 2D. Therefore, the connecting node 6 is biased in the direction that the PMOS driver 18 is always turned on, and the internal power-supply voltage int.Vcc is kicked-up in the direct current curve. FIG. 3 is a waveform diagram showing such a kick-up phenomenon. More particularly, the present inventors have noted that when the external power-supply voltage ext.Vcc level is 3V and the internal power-supply voltage int.Vcc is operated with a level of 3V, more serious problems can be generated. As a result, it has been estimated that the internal power-supply voltage supplier having the conventional internal power driver of FIG. 1 cannot be used dependably as a reliable internal power-supply voltage supplier.